FIG. 1 is an explanatory view showing circuit configuration of a conventional operational amplifier. In FIG. 1, the conventional operational amplifier 100 comprises a differential amplifier circuit 101, a level shift circuit 102, and an output circuit 103, and an output terminal OUT forms a feedback loop by being connected to one of the input terminals IN- of the differential amplifier circuit 101.
The differential amplifier circuit 101 comprises a P-channel type of MOS transistor MP101 for supplying a constant current to a differential transistor pair described below in response to input of a bias voltage VB, P-channel type of MOS transistors MP102 and MP103 forming a differential transistor pair, and N-channel type of MOS transistors MN101 and MN102 forming a current mirror circuit which functions as an active load to an amplifier.
In the differential amplifier circuit 101, the source of the MOS transistor MP101 is connected to a power line which supplies a power-supply voltage VDD (high level voltage), and the gate is connected to a terminal which supplies a bias voltage VB. The sources of MOS transistors MP102 and MP103 are connected to each other and form a differential transistor pair. Further, the sources of the MOS transistors MP102 and MP103 are connected to the drain of the MOS transistor MP101, therefore, a current supplied via the MOS transistor MP101 is supplied to the differential transistor pair consisting of the MOS transistors MP102 and MP103 as described above.
Gate of the MOS transistor MP102 is connected to one of the input terminals (inverting circuit) IN- of the differential amplifier circuit 101, however, the input terminal IN- is connected to the output terminal OUT of the operational amplifier 100 to form a feedback loop for stabilizing a gain. Gate of the MOS transistor MP103 is connected to the other input terminal IN+ (non-inverting terminal) of the differential amplifier circuit 101, and an input signal from a signal source 110 is inputted thereto.
The gates of the MOS transistors MN101 and MN102 are connected to each other while the gate and the drain of the MOS transistor MN101 are connected to each other to form a current mirror circuit. Further, the sources of the MOS transistors MN101 and MN102 are connected to a line for a ground voltage VSS (a low level voltage).
A signal from the signal source is amplified by this differential amplifier circuit 101 and is outputted from the drain of the MOS transistor MP103. Output of the differential amplifier circuit 101, namely a signal from the drain of the MOS transistor MP103 is inputted into the level shift circuit 102 and output circuit 103 in the next stage.
The output circuit 103 comprises a P-channel type of MOS transistor MP104, a N-channel type of MOS transistor MN103, and phase-compensating capacitors C1 and C2 for preventing oscillation in the MOS transistors MP103 and MN104 respectively. The drains of the MOS transistors MP103 and MN104 are connected to each other, and a node of them is connected to the output terminal OUT.
The source of the MOS transistor MP104 is connected to the line for a power-supply voltage VDD, and output from the level shift circuit 102 is inputted into the gate of the MOS transistor MP104. Thus, the MOS transistor MP103 is driven by the level shift circuit 102. On the other hand, the source of the MOS transistor MN103 is connected to the line for a ground voltage VSS with output from the differential amplifier circuit 101 inputted into the gate of the MOS transistor MN103. Thus, the MOS transistor MN103 is directly driven according to the output from the differential amplifier circuit 101.
The phase-compensating capacitor C1 is connected between the gate and the drain of the MOS transistor MP104, while the phase-compensating capacitor C2 is connected between the gate and the drain of the MOS transistor MN103. Further, a load capacitance Co is connected between the output terminal OUT and the ground voltage VSS.
FIG. 2 is an explanatory view showing a detailed circuit configuration of an operational amplifier based on the conventional technology. In order to make the description of operations clear, it is assumed herein that an operational amplifier 200 shown in FIG. 2 has a circuit configuration in which in the operational amplifier 100 shown in FIG. 1 the bias circuit 104 for driving the differential amplifier circuit 101 is added, and that the level shift circuit 102 has a circuit configuration as shown in FIG. 1. It should be noted that, the same reference numerals are assigned to components common to those shown in FIG. 1 and description thereof is omitted herein.
The bias circuit 104 comprises a constant power supply source 111, a P-channel type of MOS transistor MP105, and N-channel type of MOS transistors MN104 and MN105 forming a current mirror circuit. In the bias circuit 104, the source of the MOS transistor MP105 is connected to the line for the power-supply voltage VDD and the gate and the drain are connected to each other.
Gate of the MOS transistor MP105 is connected to the gate of the MOS transistor MP101 of the differential amplifier circuit 101, and the MOS transistors MP105 and MP101 form a current mirror circuit. With this current mirror circuit, the MOS transistor MP101 can supply a stable current to the differential transistor pair. Namely, the MOS transistor MP105 supplies the bias voltage VB shown in FIG. 1.
Gate of the MOS transistor MN104 is connected to the gate of the MOS transistor MN107 of the level shift circuit 102, and the MOS transistors MO104 and MN107 form a current mirror circuit. With this current mirror circuit, a constant current can be supplied to the MOS transistor MO107.
The level shift circuit 102 comprises P-channel type of MOS transistors MP106 and MP107 forming a current mirror circuit, a P-channel type of MOS transistor MP108, and N-channel type of MOS transistors MN106 and MN107.
In the level shift circuit 102, the gates of the MOS transistors MP106 and MP107 are connected to each other and the gate and the drain of the MOS transistor MP106 are connected to each other to form a current mirror circuit. Further, the sources of the MOS transistors MP106 and MP107 are connected to the line for the power-supply voltage VDD.
The source of the MOS transistor MP108 is connected to the line for the power-supply voltage VDD and also the gate and the drain are connected to each other. Gate of the MOS transistor MP108 is connected to the gate of the MOS transistor MO104 of the output circuit 103, and forms a current mirror circuit with the pair of the MOS transistors MP108 and MP104.
The drain of the MOS transistor MN106 is connected to the drain of the MOS transistor MP106, and the source is connected to the line for the ground voltage VSS. Gate of the MOS transistor MN106 is connected to an output terminal of the differential amplifier circuit 101, namely to the drain of the MOS transistor MP103.
The drain of the MOS transistor MN107 is connected to the drain of the MOS transistor MP108, and the source is connected to the line for the ground voltage VSS. Gate of the MOS transistor MN107 is connected to the gate of the MOS transistor MN104 to form a current mirror circuit comprising the MOS transistor MN104 in the bias circuit 104 and MOS transistor MN107.
Next, description is made for operation of an operational amplifier 200 shown in FIG. 2 centering on a current flow therein. At first, a case is considered in which a first-transitional signal is inputted from the signal source 110 to charge the load capacitance Co, namely for a transitional state where a relation between a voltage outputted from the output terminal OUT (described above VOUT hereinafter) and a voltage inputted into the input terminal IN+ (described as VIN hereinafter) is VIN&gt;VOUT. In this case, a potential at the drain of the MOS transistor MP103 is substantially at a level of the ground voltage VSS (0 V), and the MOS transistors MN106 and MN103 are cut off.
Then a potential at the drain of the MOS transistor 106 becomes close to a level of the power-supply voltage VDD, and a drain current Ip106 flowing through the MOS transistor MP106 becomes substantially zero. Because the MOS transistors MP106 and MP107 form a current mirror circuit, a drain current Ip107 flowing through the MOS transistor MP107 is supplied according to the expression Ip107={(Wp107/Lp107)/(Wp106/Lp106)}.multidot.Ip106 in proportion to the ratio of transistor sizes of the MOS transistors MP106 and MP107.
Herein Wp106 and Wp107 indicate a width of the channel of the MOS transistors MP106 and MP107 respectively, while Lp106 and Lp107 indicate a length of the channel of the MOS transistors MP106 and MP107 respectively. Herein, however, as the drain current Ip106 is nearly zero as described above, the drain current Ip107 is also almost zero.
A drain current In107 flowing through the drain of the MOS transistor MN107 is a constant current equal to a current flowing in the MOS transistor MN104, namely it is equal to a current I0 supplied from a constant current source 111 because of the fact that the MOS transistors MN107 and MN104 form a current mirror circuit. It is assumed herein, however, that the transistor size of the MOS transistor MN104 is the same as the transistor size of the MOS transistor MN107.
Although the drain current In107 is expressed as a sum of the drain current Ip107 flowing in the MOS transistor MP107 and the drain current Ip108 flowing in the MOS transistor MP108 as described above, because the drain current Ip107 is substantially zero the In107 is equal to Ip108 and the drain current Ip108 flows as the substantially drain current In107, namely as a current substantially equal to the constant current I0, to the MOS transistor MN107.
Further, because the MOS transistors MP108 and MP104 form a current mirror circuit, the drain current Ip104 flowing through the MOS transistor MP104 is obtained according to the expression Ip104={(Wp104/Lp104)/(Wp108/Lp108)}.multidot.Ip108, in proportion to the ratio of the transistor sizes of the MOS transistors MP108 and MP104.
Herein, Wp104 and Wp108 indicate a wide of the channel of the MOS transistors MP104 and MP108 respectively, while Lp104 and Lp108 indicate a length of the channel of the MOS transistors MP104 and MP108 respectively. Herein, assuming that {(Wp104/Lp104)/(Wp108/Lp108)}=n, transistor sizes of the MOS transistors MP104 and MP108 are set such that the drain current Ip104 is n times larger than the drain current Ip108. It is also assumed that, the transistor size of the MOS transistor MN103 is the same as the transistor size of the MOS transistor MP104.
Herein, because the drain current In103 in the MOS transistor MN103 is substantially zero due to input of a low-level voltage into the gate of the MOS transistor MN103 as described above, a current substantially equal to the drain current Ip104 flows through the output terminal OUT (described as IOUT hereinafter). Namely, the relational expression IOUT=Ip104=n.multidot.Ip108=n.multidot.Ip107=n.multidot.I0 holds, and charging to the load capacitance Co is achieved with this current IOUT.
Next, a case is considered in which a last-transitional signal is inputted from the signal source 110 and the load capacitance C0 is discharged, namely for a state where the relation between the output voltage VOUT and input voltage VIN is VIN&lt;VOUT. In this case, as a low-level input voltage VIN close to the ground voltage VSS is inputted into the gate of the MOS transistor MP103,a potential at the drain of the MOS transistor MN102 becomes higher than a threshold value for the MOS transistors MN103 and MN106 and the drain current In106 in the MOS transistor MN106 and the drain current In103 in the MOS transistor 103 increase.
The drain current Ip106 in the MOS transistor MP106 flows with an amplitude substantially equal to that of the drain current In106, and also the drain current Ip107 in the MOS transistor MP107 has an amplitude equal to that of the drain current Ip106 because of configuration of a current mirror circuit.
Herein, the drain current In107 in the MOS transistor MN107 can be expressed as a sum of the drain currents Ip107 and Ip108, but the drain current In107 is a constant current I0 because of the current mirror configuration consisting of the MOS transistors MN104 and MN107, so that the drain current Ip107 increases in association with increase of the drain current In106 (=drain current Ip106) while the drain current Ip108 decreases.
Decrease of the drain current Ip108 in the MOS transistor MP108 means decrease of the drain current Ip104 in the MOS transistor MP104 because of the current mirror circuit configuration. Thus, a sufficiently decreased drain current Ip104 flows through the MOS transistor MP104 as an idling current, and a current with an amplitude obtained by subtracting the drain current Ip104 from the drain current In103 flowing in the MOS transistor MN103 (In103-Ip104) is discharged as a suction current from the output terminal OUT from the load capacitance Co.
Next, a case is considered in which charging into or discharging from the load capacitance Co is not executed, namely for a state where the relation between the output VOUT and input voltage VIN is VIN=VOUT. In this case, a current is not inputted into or nor outputted from the output terminal OUT, and the relation between a drain current in the MOS transistor MP104 and that in the MOS transistor MN103 is Ip104=In103. Only in this stabilized state, a voltage inputted from the signal source 110 into the differential amplifier circuit 101 is amplified by one time, and is accurately outputted from the output terminal OUT.
Thus, in the operational amplifier 200 described above, the output is connected to the input terminal to form a feedback loop, and this circuit realizes signal amplification with a stable gain in both the transitional state such as VIN&lt;VOUT or VIN&gt;VOUT and also in the stable state of VIN=VOUT.
Herein, in the confessional type of operational amplifier like the operational amplifier 200 shown in FIG. 2, to prevent generation of troubles such as oscillation of an input signal having a high frequency or vibration to a transitional response of an input signal, generally phase-compensating capacitors C1 and C2 are provided in the output circuit.
However, in the operational amplifier 200 shown in FIG. 2, output from the level shift circuit 102 is inputted into the gate of the MOS transistor MP104 with the phase-compensating capacitor C1 provided therein, while output from the differential amplifier circuit 101 is directly inputted, not via the level shift circuit 102, into the gate of the MOS transistor MP103 with the phase-compensating capacitor C2 provided therein.
Therefore, a difference is generated between a current charged into or discharging from the phase-compensating capacitors C1 and C2, hence a cut-off state is generated in the MOS transistor MN103 or MP104, which in turn generates an overshoot or an undershoot.
FIG. 3 is an explanatory view showing a detailed circuit configuration for explaining generation of overshoot in an operational amplifier based on the conventional technology. FIG. 4 is a timing chart showing operations when overshoot is generated in the conventional type of operational amplifier. FIG. 3 shows a flow of a discharged current from the phase-compensating capacitors C1 and C2 when a signal indicating a rapid first transition is inputted especially to the input terminal IN+.
In FIG. 3, at first, when an input signal with a quick first-transitional speed is inputted into the gate of the MOS transistor MP103, namely the step input SP as shown in FIG. 4 is loaded thereto, because of the difference between the timing of the first transition of output, only the MOS transistor MP103 is cut off for a certain period of time with the MOS transistor MP102 kept ON.
In the bias circuit 104, as described above, with a current mirror circuit consisting of the MOS transistors MN104 and MN105 as well as with the MOS transistor MP105, a constant current I0 supplied from a current source 111 flows as a drain current to the MOS transistor MP101 in the differential amplifier circuit 101. This constant current I0 is supplied to a differential transistor pair consisting of the MOS transistors MP102 and MP103, but as the MOS transistor MP103 is OFF, the constant current I0 flows via the MOS transistor MP102 which is in an ON state to the MOS transistor MN101.
When the constant current I0 flows into the MOS transistor MN101, it is necessary that the constant current I0 also flows as a drain current into the MOS transistor MN102 due to an action of the current mirror circuit. Herein, as the MOS transistor MP103 is in the cut-off state, the drain current equivalent to constant current I0 for the MOS transistor MN102 is extracted from the phase-compensating capacitor C2 of the output circuit 103 which is connected to the drain of the MOS transistor MN102. Namely, because of the charge, the phase-compensating capacitor C2 is driven by the constant current I0.
On the other hand, as the MOS transistor MN104 in the bias circuit 104 and the MOS transistor MN107 in the level shift circuit 102 form a current mirror circuit, it is required that, the constant current I0 flows as a drain current in the MOS transistor MN107 also. A drain current from the MOS transistor MN107 is expressed as a sum of the drain current Ip108 in the MOS transistor MP108 and a current extracted from the phase-compensating capacitor C1. Namely, because of the chagre, the phase-compensating capacitor C1 is driven by the constant current I1=(I0-Ip108).
Herein, assuming that the capacitance of the phase-compensating capacitor C1 is equal to that of the phase-compensating capacitor C2, in a case of I0&gt;I1 as shown in FIG. 4, in a quick first transition of an input signal, a period HZ for which the MOS transistor MN103 is kept OFF is generated and an overshot OS is generated until the MOS transistor MN103 is again turned ON.
On the other hand, assuming that the capacitance of the phase-compensating capacitor C1 is equal to that of the phase-compensating capacitor C2, in a case of I0&lt;I1, in a quick last transition of an input signal, a period for which the MOS transistor MP104 is cut OFF is generated and an undershoot is generated until the MOS transistor MP104 is again turned ON.
When a value of overshoot or undershoot, namely a component of the minimum output error voltage off from the specified output voltage becomes large, a time required until the output voltage is stabilized to the specified level becomes too long, which makes it impossible to quickly obtain stabilized amplified output.
This problem that a difference between a driving current for the phase-compensating capacitor C1 and that for the phase-compensating capacitor C2, namely a difference in a particular time constant can be solved by equalizing the driving capacity I1 of the level shift circuit 102 to the driving capacity I0 of the differential transistor pair, and this method is not effective when a capacity value of the load capacitance Co is large.
Namely, generally as a time constant for the load capacitance Co is set equal to a time constant for the phase-compensating capacitor C1, a relation C1.multidot.VOUT/(I0-Ip108)=Co+VOUT/n.multidot.Ip108 holds, and the current Ip108 is expressed by the expression Ip108=Co.multidot.I0/(Co+C1.multidot.n). Therefore, when Co becomes larger the current Ip108 becomes unignorable, and the relation I0&gt;I1 is established, so that a difference between a time constant for the phase-compensating capacitor C1 and that for the phase-compensating capacitor C2 is generated.